PODUEL, B.; KANSAKAR, P.; CHHETRI, S. R.; JOSHI, S. R. Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL. Nepal Journal of Science and Technology, [S. l.], v. 15, n. 1, p. 81–88, 2015. DOI: 10.3126/njst.v15i1.12021. Disponível em: https://www.nepjol.info/index.php/NJST/article/view/12021. Acesso em: 23 feb. 2024.